1. Field of the Invention
The present invention generally relates to an exchange in a B-ISDN (Broad-band Integrated Services Digital Network), and more particularly to an address decision system having an address check system for determining whether or not an error is contained in an address signal output by the address check system.
2. Description of the Prior Art
In the B-ISDN, the unit of communications is an ATM (Asynchronous Transfer Mode) cell which contains information to be transferred. Each ATM cell is managed using routing information (tag information) and policing information. The routing information is used for routing the ATM cell being considered; policing information is used for defining a frequency band within which the ATM cell being considered is transferred. The routing information and the policing information are managed in a VPI/VCI (Virtual Path Identifier/Virtual Channel Identifier) unit or segment. The VPI/VCI is one of the elements which form the ATM cell.
FIG. 1 shows a format of an ATM cell prescribed in the CCITT Recommendation I. 361, the disclosure of which is hereby incorporated by reference. The ATM cell consists of 53 bytes. FIG. 1(a) shows the format of the entire ATM cell, and FIG. 1(b) shows a 48-byte information field contained in the ATM cell. The above-mentioned VPI/VCI segment is one of the elements which form an ATM header which is concatenated to the information field. As shown in FIG. 2, 16-bit tag information TAG is concatenated to the leading end of the ATM cell. The tag information represents routing information for switching the ATM cell.
Data management in the VPI/VCI unit is carried out, at the time of setting up a call, by writing the VPI/VCI segment of the above call into a VPI/VCI table memory. When the call is released, the VPI/VCI of the call is deleted from the VPI/VCI table memory under control of a call processor (not shown). Information can be managed on the basis of address information concerning the VPI/VCI table memory. Hence, information can be substantially managed in the VPI/VCI unit. The address of the VPI/VCI table memory can be obtained by the VPI/VCI of the cell by use of hardware, without software. This contributes to speeding up cell processing.
FIG. 3 shows an address decision system in an ATM exchange. The address decision system comprises a VPI/VCI latch circuit 2, a VPI/VCI table memory 3, a simultaneous comparator circuit 4, and an address decision circuit 5. The VPI/VCI latch circuit 2, which is connected to a cell highway 1, extracts a VPI/VCI from each cell transferred via the cell highway 1, and latches it therein. The VPI/VCI table memory 3 stores the VPI/VCI value of cells which is set at the time of setting up a call. More specifically, the VPI/VCI table memory 3 stores addresses and VPI/VCI values specified by the addresses. It will now be assumed that n pieces of data (n VPI/VCI values) are stored in the VPI/VCI table memory 3.
The comparator circuit 4 simultaneously compares all the VPI/VCI values stored in the VPI/VCI table memory 3 with the VPI/VCI value latched in the VPI/VCI latch circuit 2. The address decision circuit 5 executes an address encoding process using output signals of the comparator circuit 4. The encoded address output by the address decision circuit 5 consists of m bits. The m-bit encoded address serves as an address signal of predetermined table memories (not shown).
During operation, the VPI/VCI latch circuit 2 extracts the VPI/VCI value from the cell transferred via the cell highway 1, and latches it therein. The comparator circuit 4 compares the VPI/VCI value latched in the latch circuit 2 with all the VPI/VCI values stored in the VPI/VCI table memory 3. This simultaneous comparison process contributes to speeding up cell processing.
The VPI/VCI table memory 3 stores one VPI/VCI value specified by one address. Hence, only one of the n comparison results output by the comparator circuit 4 shows address matching. The address decision circuit 5 encodes the n bits output by the comparator circuit 4, and generates the encoded address signal consisting of m bits. The m-bit address signal is used as an address signal for accessing predetermined table memories (not shown).
If there is no fault or error, only one of the n bits output by the comparator circuit 4 shows the address matching. However, due to a fault occurring in the network, the address decision circuit 5 may generate an erroneous output signal. For example, a plurality of bits among the n bits from the comparator circuit 4 may show the address matching. The conventional address decision system shown in FIG. 3 does not have any means for detecting whether or not the m-bit address signal has an error.